1. Field of the Invention
The present invention relates to a flash memory. In particular, the present invention discloses a flash memory capable of utilizing one driving voltage output circuit to drive a plurality of word drivers.
2. Description of the Prior Art
Recently, demand for portable devices has been boosted incredibly. The technology and application fields associated with the flash memory are accordingly developed. These portable devices include films of digital cameras, cellular phones, video game apparatus, personal digital assistants, answering machines, programmable ICs, and etc. The flash memory is a non-volatile memory, and the flash memory operates through adjusting a threshold voltage for effecting formation of a channel when storing data. Therefore, not only are the data stored, but also the data kept in the flash memory do not need to be flushed after the flash memory is disconnected from a power supply.
Please refer to FIG. 1, which is a structure diagram of a prior art flash memory 10. The flash memory 10 has a substrate 12, a source 14, a drain 16, a floating gate 18, and a control gate 20. A channel 22 induced between the floating gate 18 and the substrate 12 is isolated from the floating gate 18 through an oxide layer 24. Furthermore, another oxide layer 25 isolates the control gate 20 and the floating gate 18. The substrate 12 is electrically connected a reference voltage Vbb. If the flash memory 10 has an NMOS-based structure, the substrate 12 is a p-doped area, and the source 14 and the drain 16 are n-doped areas. On the contrary, if the flash memory 10 has a PMOS-based structure, the substrate 12 is an n-doped area, and the source 14 and the drain 16 are p-doped areas. Please note that only one memory cell 26 is shown in FIG. 1 for simplicity. However, the flash memory 10 generally has many memory cells 26 indexed by rows and columns. That is, a memory cell 26 located at an intersection of one row and one column corresponds to a memory address for storing data.
The operation of the flash memory 10 is described as follows. Taking the flash memory 10 with the NMOS-based structure for example, the control voltage Vcg inputted to the control gate 20 is capable of altering a total amount of electrons stored on the floating gate 18. Therefore, the electrons stored on the floating gate 18 can be used to adjust the threshold voltage associated with formation of the channel 22. When a reading operation is performed, data bit stored by the memory cell 26 is detected to be “1” or “0” according to the total amount of electrons stored on the floating gate 18. When the floating gate 18 keeps much more electrons, the threshold voltage associated with the channel 22 is increased owing to negative polarity provided by the floating gate 18. That is, a voltage level of the control gate 20 needs to be pumped to a higher positive voltage to overwhelm a negative voltage level provided by the floating gate 18 for inducing the channel 22 on the substrate 12. On the contrary, when the floating gate 18 keeps fewer electrons or no electrons, the threshold voltage associated with formation of the channel 22 is accordingly low. Generally speaking, in order to conduct the source 14 and the drain 16, that is, to induce the channel 22 between the source 14 and the drain 16 for performing the reading operation, the control voltage Vcg is applied to the control gate 20. Then, the current passing through the source 14 and the drain 16 is measured to determine whether the data bit stored by the memory cell 26 is “1” or “0”.
Operations associated with the flash memory 10 are divided into a programming operation, a reading operation, and an erasing operation. Taking the flash memory 10 having the NMOS-based structure for example, the reference voltage Vbb electrically connected to the substrate 12 corresponds to a grounding voltage (0V for instance), the control voltage Vcg electrically connected to the control gate 20 corresponds to a positive voltage (+8.5V for instance), the control voltage Vs electrically connected to the source 14 corresponds to the grounding voltage, and the control voltage Vd electrically connected to the drain 16 corresponds to a positive voltage (+5V for instance) when the programming operation is started. The channel 22 is successfully induced now to connect the drain 16 and the source 14, and electrons flow from the source 14 to the drain 16. Because a voltage difference between the drain 16 and the source 14 is great, a strong electric field is established to drive electrons within the channel 22, and well-known channel hot electrons are accordingly induced. When the energy of the channel hot electrons is high enough to overcome a potential barrier established by the oxide layer 24, the control gate 20 then attracts the energized channel hot electrons to the floating gate 18. That is, the floating gate 18 is programmed to store a predetermined amount of electrons through the programming operation. With regard to the memory cell 26 without being programmed, the grounding voltage is used to drive the control gate 20 so that the channel 22 is impossible to be induced. In other words, the floating gate 18 is unable to store a predetermined amount of electrons.
With regard to the reading operation, the reference voltage Vbb inputted to the substrate 12 corresponds to a grounding voltage (0V for instance), the control voltage Vcg inputted to the control gate 20 corresponds to a positive voltage (+3.3V for instance), and the control voltage Vd inputted to the drain 16 corresponds to a positive voltage (+1V for instance). If the floating gate 25 now has kept a predetermined amount of electrons through the above-mentioned programming operation, the control voltage Vcg is not high enough to make the channel 22 induced in the substrate 12. Therefore, the source 14 and the drain 16 are not capable of conducting current successfully. On the contrary, if the floating gate 25 does not keep a predetermined amount of electrons through the above-mentioned programming operation yet, the control voltage Vcg is high enough to induce the channel 22 within the substrate 12. Therefore, the source 14 is successfully connected to the drain 16 with the help of the induced channel 22. In other words, current is successfully passed through the source 14 and the drain 16. In the end, a prior art sense amplifier is activated to determine the logic value (“1” or “0”) recorded by the memory cell 26 according to magnitude of the passing current.
With regard to the erasing operation, the reference voltage Vbb electrically connected to the substrate 12 corresponds to a positive voltage (+8.5V for example), the control voltage Vcg electrically connected to the control gate 20 corresponds to a negative voltage (−7V for example), the control voltage Vs electrically connected to the source 14 corresponds to a grounding voltage (0V for example), and the drain 16 is floating. If the floating gate 25 has stored a predetermined amount of electrons, the electric field established between the control gate 20 and the substrate 12 will expel the electrons out of the floating gate 25. In other words, a well-known Fowler-Nordheim tunning effect occurs to remove the electrons on the floating gate 25 and the expelled electrons are drained out through the drain 14.
As mentioned above, the control gate 20 needs to be driven by a suitable control voltage Vcg no matter if the flash memory 10 performs the programming operation, the reading operation, or the erasing operation. Generally speaking, the control gate 20 is electrically connected to a word line. Therefore, a driving circuit is necessary to provide the word line with an appropriate operating voltage. Please refer to FIG. 2, which is a circuit diagram of the flash memory 10 shown in FIG. 1. The flash memory 10 has a first decoder 32, a second decoder 34, a row driver 36, a power supply circuit 38, and a plurality of memory blocks 40a, 40b. The row driver 36 includes a plurality of word line drivers 42a, 42b, and each of the word line drivers 42a, 42b has a plurality of word lines WL0-Wln. In addition, each of the word lines WL0-Wln is electrically connected to a plurality of memory cells 44. The first decoder 32 is used to decode a memory address ADDRESS for generating a first decoding signal XP. The first decoding signal XP is used to determine which word line driver 42a, 42b is selected. For example, the memory address ADDRESS corresponds to one memory cell 44 located at the memory block 40a. After the first decoder 32 decodes the memory address ADDRESS, the first decoder 32 acknowledges that the word line driver 42a needs to be activated for accessing the memory block 40a owing to the relationship between the memory address ADDRESS and the memory block 40a, and the first decoding signal XP is then issued by the first decoder 32 to select the wanted word line driver 42a. 
In addition, the second decoder 34 also decodes the memory address ADDRESS for generating a second decoding signal XT. The second decoding signal XT is used to determine which word line needs to be driven by a specific operating voltage for programming, reading, or erasing a predetermined memory cell. For instance, the memory address ADDRESS corresponds to a memory cell 44 located at the word line WL0 within the memory block 40a. If the flash memory 10 starts a reading operation, the control gate of the memory cell, as mentioned above, needs to be driven by a voltage equaling +3.3V. Therefore, when the first decoding signal XP selects the word line driver 42a, and the second decoding signal XT selects the word line WL0, the word line driver 42a is capable of driving the word line WL0 to approach a voltage level equaling +3.3V.
The power supply circuit 38 is used to provide the row driver 36 with required operating voltages. For example, when the flash memory 10 performs the programming operation, the power supply circuit 38 outputs a voltage equaling +8.5V to the control gate of a memory cell 44 if the memory cell 44 needs to be programmed. On the contrary, if the memory cell 44 does not need to be programmed, the power supply circuit 38 outputs a voltage equaling 0V to the control gate of the memory cell 44. When the flash memory 10 performs the reading operation, the power supply circuit 38 outputs a voltage equaling +3.3V to the control gate of the memory cell 44 if the memory cell 44 needs to be read. On the contrary, if the memory cell 44 does not need to be read, the power supply circuit 38 outputs a voltage equaling 0V to the control gate of the memory cell 44. When the flash memory 10 performs the erasing operation, the power supply circuit 38 outputs a voltage equaling −7V to the control gate of the memory cell 44 for erasing data stored on the memory cell 44. To sum up, the power supply circuit 38 provides the row driver 36 with different voltage levels according to the programming operation, the reading operation, or the erasing operation currently run by the flash memory 10.
Please refer to FIG. 3, which is a circuit diagram of the word line driver 42a shown in FIG. 2. The word line driver 42a includes an NAND gate 46 and a plurality of NOR gates 48a, 48b, 48c. As mentioned above, the first decoding signal XP outputted from the first decoder 32 is used to select one word line driver within the roe driver 36. Suppose that the row driver 36 has 8 word line drivers, wherein the word line driver 42a is the 1st word line driver, and the word line driver 42b is the 8th word line driver. It is well-known that three decoding signals XPA, XPB, XPC can be used to select one word line driver out of 8 word line drivers. For example, the signals inputted into the NAND gate 46 are an inverted signal of the decoding signal XPA, an inverted signal of the decoding signal XPB, and an inverted signal of the decoding signal XPC respectively. Therefore, the word line driver 42a can be chosen successfully when all of the three decoding signals XPA, XPB, XPC correspond to the same logic value “0”. Concerning each word line driver, the circuit structure is similar to that of the word line driver 42a. The only difference is that the signals inputted into the NAND gate 46. Taking the word line driver 42b for example, the signals inputted into the NAND gate 46 are decoding signals XPA, XPB, XPC. Therefore, the word line driver 42b can be chosen successfully when all of the three decoding signals XPA, XPB, XPC correspond to the same logic value “1”.
To sum up, which word line driver being selected out of the 8 word line drivers depends on logic values of the decoding signals XPA, XPB, XPC. As shown in FIG. 3, each of the NOR gates 48a, 48b, 48c corresponds to a specific word line. That is, the word line drivers 42a has 8 NOR gates, wherein the NOR gate 48a corresponds to the word line WL0, the NOR gate 48b corresponds to the word line WL1, and the NOR gate 48c corresponds to the word line WL7. The second decoding signal XT is used to determine which word line needs to be driven by an operating voltage for successfully programming, reading, or erasing a predetermined memory cell. Because the word line driver 42a shown in FIG. 3 has 8 word lines WL0-WL7, the second decoding signal XT comprises 8 decoding signals XT0-XT7 when the second decoder 34 outputs the second decoding signal XT. A logic value of each decoding signal XT0-XT7 is used to determine whether a corresponding word line is selected or not. For instance, if a control gate of the predetermined memory cell is electrically connected to the word line WL0, the decoding signal XT0 corresponds to the logic value “1” only, but remaining decoding signals XT1-XT7 correspond to the logic value “0”. As shown in FIG. 3, after the word line driver 42a is selected through the decoding signals XPA, XPB, XPC corresponding to the logic value “0”, an output port of the NOR gate 48a corresponding to the logic value “1” if the decoding signal XT0 corresponds to the logic value “1”. With regard to other decoding signal such as the decoding signal XT1, the output port of the NOR gate 48b corresponds to the logic value “0” because the logic value associated with the decoding signal XT1 is “0”.
Please note that a level shift circuit is interposed between an output port of each NOR gate and a corresponding word line WL0-WL7. As shown in FIG. 3, the NOR gate 48a is electrically connected to the level shift circuit 50a, the NOR gate 48b is electrically connected to the level shift circuit 50b, and the NOR gate 48c is electrically connected to the level shift circuit 50c. The level shift circuits 50a, 50b, 50c apply the same circuit structure. Taking the level shift circuit 50a for example, the level shift circuit 50a has transistors 52a, 52b, 52c, 52d and an inverter 54, wherein the transistors 52a, 52c are PMOS transistors, and the transistors 52b, 52d are NMOS transistors. Suppose that the flash memory 10 runs the reading operation. Therefore, the power supply circuit 38 respectively outputs +3.3V and 0V. The voltage level +3.3V is used to be the voltage level V1 shown in FIG. 3, and the voltage level 0V is used to be the voltage level V2 shown in FIG. 3. When an output port of the NOR gate 48a corresponds to the logic value “1”, the transistor 52b is turned on for driving a node A to approach 0V. That is, the node A corresponds to the logic value “0”.
At the same time, the transistor 52c is turned on to make a node B approach a voltage level equaling 0V. That is, the node B corresponds to the logic value “1”. Because the transistors 52a, 52d are not turned on, the word line WL0 finally approaches a voltage level equaling +3.3V for successfully reading data stored by the memory cell. On the contrary, when the output port of the NOR gate 48a corresponds to the logic value “0”, the transistor 52b is turned off without conducting current, but an output port of the inverter 54 corresponds to the logic value “1” to turn on the transistor 52d. Therefore, a node B approaches a voltage level equaling 0V. That is, the node B corresponds to the logic value “0”. At the same time, the transistor 52a is turned on to make the node A approach a voltage level equaling +3.3V. That is, the node A corresponds to the logic value “1”. Because the transistors 52b, 52c are not turned on, the word line WL0 finally approaches a voltage level equaling 0V so that the corresponding memory cell can not be read with such a low voltage.
As mentioned above, each of the word lines WL0-WL7 needs to be connected to a corresponding level shift circuit. Taking the level shift circuit 50a for example, the level shift circuit 50a determines the word line WL0 being driven to approach the voltage level V1 or the voltage level V2 according to the decoding signals XPA, XPB, XPC, XT0. It is obvious that the level shift circuit 50a requires at least 6 transistors to enable its logic function. Therefore, when the prior art flash memory 10 has a plurality of word lines, the amount of transistors used in the row driver 36 is huge, making the chip size of the flash memory 10 accordingly large.